1. Field of the Invention
The present invention relates to a receiver for receiving satellite broadcasting which transmits digitally compressed video and audio information digitally modulated by QPSK (quadrature phase shift keying) modulation, for example, and more particularly, it relates to a tuner part for receiving signals of the 1 GHz band from an antenna (LNB: low noise block downconverter) and selecting a channel.
2. Description of the Background Art
Satellite television broadcast systems can be divided into an analog FM system which frequency-modulates analog video and audio signals and a digital modulation system which digitizes and compresses analog video and audio signals and digitally modulates the compressed data by QPSK modulation or the like for transmitting the same.
Due to the development of the semiconductor technique and the digital image compression technique, it is nowadays possible to transmit a larger number of television programs by the digital modulation system in the same frequency band as compared with the analog FM system. Therefore, digital modulation satellite broadcasting is employed or planned at present. Also in relation to CATV (cable television) and ground wave broadcasting, employment of the digitization system is discussed.
FIG. 35 is a block diagram showing a part 402 for making a transport output in a digital DBS (direct broadcasting satellite) receiver 400. The term "transport output" indicates a data format defined by the MPEG standard for transmission/reception of data compressed in the MPEG standard. Video and audio data are multiplexed in the transport output.
Referring to FIG. 35, the transport output part 402 includes an RF (radio frequency) signal input terminal 60, a tuner circuit 410 for selecting a signal of a certain single channel from RF signals and converting the same to an intermediate frequency (hereinafter referred to as IF) signal, an I/Q demodulator 412 for demodulating baseband signals including I (in-phase) and Q (Quadrature-phase) signals from the IF signal, and a QPSK demodulator+FEC part 414 for digitally processing outputs of the I/Q demodulator 412, performing error detection, error correction etc. and obtaining the transport output.
The QPSK demodulator+FEC part 414 includes an A/D converter circuit 416 for digitizing the baseband signals outputted from the I/Q demodulator 412, a QPSK demodulator 418 for QPSK-demodulating outputs of the A/D converter circuit 416, a Viterbi decoder 420 for Viterbi-decoding outputs of the QPSK demodulator 418, and a Reed-Solomon error correcting circuit 422 for error-correcting outputs of the Viterbi decoder 420 by Reed-Solomon coding.
The Viterbi decoding is one technique for detecting the most probable series in case of receiving data series recorded with data-to-data correlation. The feature of the Viterbi decoding resides in that the original data series is easy to detect even when the data include noise. The Reed-Solomon coding is one error correction coding methods for transmitting/receiving data with the addition of data for error correction.
The QPSK demodulator 418 and the I/Q demodulator 412 are controlled by a microcomputer 404.
FIG. 36 shows the block structure of the conventional tuner part 408 along with the relation between a chassis for shielding and a substrate. In the following description including that of FIG. 36, it is assumed that the respective circuits are clearly divided into blocks, simply for the purpose of convenience. In practice, the circuits are not so clearly divided into blocks.
Referring to FIG. 36, the tuner part 408 includes an IF signal demodulator part or tuner circuit 410 for selecting a signal of a single channel from RF signals of the 1 GHz band consisting of a plurality of channels received from an LNB of an antenna, amplifying this signal and converting the same to an IF signal, and an I/Q signal demodulator part 412 for demodulating I and Q signals which are baseband signals by demodulating the IF signal outputted from the IF signal demodulator part 410. The IF signal demodulator part 410 and the I/Q signal demodulator part 412 are formed on the same substrate 432, and stored in a single chassis 430.
The IF signal demodulator part 410 includes an RF signal input circuit 90 which is connected to receive the RF signals from the RF signal input terminal 90, a frequency selector circuit 96 for oscillating a first local oscillation signal for selecting a signal of a certain single channel from the RF signals, an IF signal converter circuit 92 for mixing the first local oscillation signal with the RF signal for converting the same to an IF signal, an amplifier circuit 94 for amplifying the IF signal at an amplification factor which is decided by a supplied AGC (Auto Gain Control) voltage and controlling the same to a prescribed bandwidth for outputting this signal, and an AGC control circuit 98 for controlling a signal attenuation factor in the RF signal input circuit 90 and the signal amplification factor in the amplifier circuit 94 on the basis of an AGC control voltage (AGC IN) supplied from a terminal 78. The AGC control voltage is supplied from an integrated circuit for PSK/QPSK demodulation which will be described later.
This tuner part 408 has an input terminal 66 for applying supply voltage to the LNB, source voltage terminals 68 and 70 for supplying source voltages, terminals 72 and 74 for supplying data for specifying a selected frequency from the microcomputer and a clock signal, respectively and a terminal 76 for supplying a tuning voltage (28 V).
The I/Q signal demodulator part 412 includes a second oscillator circuit 112 for outputting a second local oscillation signal having a frequency substantially identical to the frequency of the IF signal, a 90.degree. phase shifter 114 for producing two oscillation signals which are 90.degree. out of phase with each other from the second local oscillator circuit 112, a baseband converter circuit 116 for mixing the IF signal received from the amplifier circuit 94 with the two oscillation signals from the 90.degree. phase shifter 114 with each other, converting the same to baseband signals consisting of I and Q signals and outputting these signals, and an amplifier circuit 118 for amplifying the I and Q signals outputted from the baseband converter circuit 116 respectively and outputting the same to I/Q signal output terminals 62 and 64. The I/Q signal demodulator part 412 further has terminals 84, 86 and 88 for supplying prescribed source voltages.
The terminals 72 and 74 are connected to the microcomputer 404 (not shown in FIG. 36) shown in FIG. 35.
Referring to FIG. 36, the RF signals inputted in the RF signal input terminal 60 are supplied to the IF signal converter circuit 92 through the RF signal input circuit 90. These RF signals are mixed with the first local oscillation signal which is outputted from a first local oscillator included in the frequency selector circuit 96, whereby the IF signal converter circuit 92 outputs IF signals having frequencies defined by the frequency differences between the RF signals and the first local oscillation signal. At this time, the frequency of the first local oscillation signal outputted from the frequency selector circuit 96 is locked on the basis of channel data supplied from the microcomputer 404. Thus, the IF signal converter circuit 92 selects only one channel.
The IF signal is amplified by the amplifier circuit 94 and bandwidth-limited to become a signal having a frequency of 479.5 MHz, further level-controlled in accordance with a control voltage from the AGC control circuit 98, and guided to the I/Q signal demodulator part 412.
The second local oscillator 112 generates a second local oscillation signal having the same frequency as the IF signal. The 90.degree. phase shifter 114 produces signals which are 90.degree. out of phase with each other from the second local oscillation signal, and supplies the same to the baseband converter circuit 116. The baseband converter circuit 116 mixes the IF signal with the two oscillation signals which are 90.degree. out of phase with each other respectively, and extracts phase information from the IF signal, thereby obtaining I and Q signals which are baseband signals.
The I and Q signals are amplified by the amplifier circuit 118 to proper levels respectively, supplied to a subsequent circuit (QPSK demodulator part) from the I/Q signal output terminals 62 and 64, to be QPSK-demodulated.
As hereinabove described, the second local oscillation signal generated from the second local oscillator 112 in the I/Q signal demodulator part 412 is made to have the same frequency as the IF signal, in order to demodulate the IF signal. Further, the IF signal demodulator part 410 and the I/Q signal demodulator part 412 are formed on the same single substrate 432, and stored in the single chassis 430. Thus, the IF signal demodulator part 410 and the I/Q signal demodulator part 412 share a ground pattern.
Therefore, the second local oscillation signal from the second local oscillator 112 of the I/Q signal demodulator part 412 may be mixed into the IF signal demodulator part 410 through a power supply line, a signal line and the ground pattern on the common substrate 432. Since the 90.degree. phase shifter 114 and the AGC control circuit 98 are arranged on the same substrate 432 in proximity to each other, further, a harmonic twice or three times the second local oscillation signal from the second local oscillator 112 may be mixed into the AGC control circuit 98 from the 90.degree. phase shifter 114 through a floating capacitance, and inputted in the RF signal input terminal 60 through the circuits in the IF signal demodulator part 410.
If the RF signal selected in the IF signal converter circuit 92 has the same frequency as this harmonic in this case, the unnecessary harmonic interferes with the originally required normal IF signal, leading to inferior QPSK modulation. In case of digital broadcasting, such inferior demodulation results in data loss to mosaic the screen, and the picture quality is heavily deteriorated as compared with the analog system. Therefore, such interference is preferably eliminated to the minimum.
For example, the second local oscillator 112 oscillates at 479.5 MHz. Harmonics twice, three times and four times this frequency are 959 MHz, 1438.5 MHz and 1918 MHz respectively. Spurious responses are caused at input frequencies in the range of .+-.10 MHz with respect to these frequencies. In case of the harmonic having the frequency of 959 MHz, for example, a spurious response is caused in the range of input frequencies of 949 MHz to 969 MHz.
While the AGC control circuit 98 of the IF signal demodulator part 410 is supplied with the AGC control voltage from the QPSK demodulator part, it is necessary to quicken the response of AGC control through the AGC control circuit 98 and the amplifier circuit 94, in order to perform QPSK demodulation in an excellent state.